Carrier assemblies of organic laminate composite materials are increasingly used as high density and high performance electronic multi-chip modules and single chip modules. Common methods to attach the chips to the carrier board include controlled collapse chip connect, flip chip attach, and wire bonding methods.
Controlled collapse chip connect (C4) uses interconnection pads positioned in a peripheral or area array on the face of a semiconductor chip. These interconnection pads typically are mounds or hemispherical bumps coated with high melting point lead solder. The semiconductor chip is then positioned on a carrier having a corresponding array. The solder bumps of the semiconductor chip in contact with these pads are reflowed; melting of the solder bumps induces bond formation via metallurgical reaction and wetting of the solder to the carrier pad surfaces to form solder joints. Upon cooling the solder joints solidify and electrical and mechanical interconnections are is produced.
Flip chip attach uses peripheral or area array of interconnection pads similar to those used for controlled collapse chip connect but solder bumps may or may not be present on the semiconductor chip. The chip is inverted or "flipped" so that the semiconductor device pads align with corresponding pads on the carrier to which the chip is attached. Bonding and electrical contact is established using several methods, such as the use of conductive adhesives or solder, or welding, or other methods which form either metallurgical or adhesive bonds between the semiconductor pads to the carrier pads. For flip chip attach, solder bumps, if present on the chip, are generally not reflowed.
Wire bonding is also used to establish an electrical connection between the semiconductor chip and the carrier. Wires are ultrasonically bonded from the semiconductor chip pads to pads on the carrier. The semiconductor device could be mounted with adhesive or with solder onto the carrier.
In general, use and selection of a given chip attach method is in pall determined by carrier materials temperature compatibility. For example, C4 of chips with high lead (Pb) bumps is not viable as an attachment method on some flexible circuits or fiberglass reinforced circuit boards. Temperatures required for the C4 attach exceed the decomposition temperatures of many adhesives required for lamination of flexible circuit layers. Similarly, the C4 process temperatures also exceed decomposition temperatures of most epoxies used as the matrix material in fiberglass reinforced rigid printed circuit boards. For chip on board compatibility on these flexible printed circuit or printed circuit board materials wirebonding processes are generally used. In order to provide compatibility with these flexible printed circuit or printed circuit board materials, however, a low melting point alloy must be present on either carrier pad surfaces or on the semiconductor chip solder bumps.
The methods devised to apply a small uniform volume of the low melting point solder onto the carrier or onto the interconnects of the semiconductor device typically are complex and require specialized tools. U.S. Pat. No. 5,251,806 entitled "Method of Forming Dual Height Solder Interconnection" to Agarwala et al., is a method of providing a semiconductor chip with a bump structure of low melting point solder on top of a high melting point solder bump. The dry processing technique of '806 with vapor deposition and sputtering alters the geometry of the solder bump to increase the integrity of the connection. U.S. Pat. No. 5,244,143 to Ference et al. entitled, "Apparatus and Method for Injection Molding Solder and Applications Thereof" provides a process known as molten solder inject in which molten solder is dispensed under pressure through a heated nozzle attached to a pattern of apertures which is aligned to either semiconductor chip or carrier surfaces. Subsequent cleaning, bump flattening, recleaning, and independent fluxing operations are then necessary to finalize the flip chip attachment assembly.
U.S. Pat. Nos. 5,299,730 and 5,410,805 to Pasch et al. disclose the attachment of semiconductor chips possessing high melt solder bumps to cards with low melt solder deposits with specific consideration given to flux containment using a preform sandwich. Methods of providing the solder-on-solder structure are not disclosed.
Another technique-to attach a semiconductor device having an array of raised high melting point solder bumps to an organic carrier involves first electroplating the organic carrier with a low melting point solder, such as tin/lead (Sn/Pb). The use of card platings, however, is expensive and has solderability restrictions such as short shelf life. The electroplating technique, moreover, is not conducive to easily reworking and/or replacing any semiconductor device on the carrier. The depth of the electroplating is relatively thin and the electroplated material forms an alloy with higher melting point characteristics when attachment reflow occurs. Depending upon the plating material used and the extent of alloy formation, removal and replacement of a semiconductor device may damage the carrier, and the interconnection pad sites may have to be redressed.
In view of the shortcomings of the methods presently used, a need exists for a simpler method to provide metallurgically active bond structures on the electrical interconnects of an electronic component, such as a semiconductor device and its carrier, and for a method that is thermally compatible with the carrier materials, especially in the field of high density single chip module/multi chip module manufacturing.
One object of the invention is to provide a cost effective method to coat area array interconnects on semiconductor devices with low melting point solder using commonly available tools in the semiconductor chip assembly industry. The object is realized by transferring the solder or other metallurgical paste with in situ stencil placement, printing, and reflow of solder paste onto area array interconnects.
It is yet another object of the invention to attach semiconductor devices to carriers comprised of materials that are incompatible with standard C4 reflow processes and associated reflow temperatures. By applying low melting point solder or other metallurgical paste onto the area array interconnects on the carrier, thermal compatibility is achieved which yields the additional advantage of greater flexibility with surface treatment of the interconnects.
It is still another object of the invention to provide a bond structure that facilitates removal of semiconductor devices and recycling of the remaining semiconductor/carrier assemblies. The object is achieved by the presence of a layer of low melting point solder on the semiconductor device interconnects because reheating and remelting this layer permits easy removal of defective or obsolete semiconductor devices from carrier surfaces at temperatures that don't damage the carrier.
Yet another object of the invention is to provide bond structures that facilitate simple replacement of semiconductor devices and carrier rework compatible with materials comprising the carrier to which replacement devices are to be attached. Once a semiconductor device is removed as described above, reattachment of replacement semiconductor devices is easy if the replacement devices have the bond structure of the invention. Again, the layer of low melting point solder on the semiconductor device interconnects permits the use of reattachment processes that are compatible with the carrier materials.
It is still another object of one embodiment of the invention to provide the bond structure on the semiconductor device rather than the carrier. An additional advantage is that the placement of the semiconductor device onto the carrier is more stable and, prior to reflow attachment, misalignment is avoided. Also, as opposed to processes where low melting point solder is directly applied to the carrier, the process step of flattening the carrier solder is eliminated.
It is yet another object of the invention to provide a process which can be used with both semiconductor devices or chips and wafers. The process herein permits device customization and high volume wafer fabrication of devices because the process to make the bond structure is compatible with low temperature flip chip attachment and rework requirements.
It is yet another object of the invention to use screen printing to coat low melting point solder or metallurgical paste onto electrical and/or mechanical interconnects having different geometries. The conductive materials forming part of the interconnects have a melting point higher than the solder or metallurgical paste. When a layer of low melting point solder is melted onto raised interconnects, a standoff between the semiconductor device and the carrier is created. This standoff decreases susceptibility of the interconnect to thermal fatigue which, of course, extends the life of solder joint.
It is yet another object to use a stencil or screen printing process in which the stencil and substrate materials are compatible with the electronic devices, the metallurgical paste, and the carriers during the elevated temperature exposure required for low melting point metallurgical paste reflow.